The main goal of the article is to present the concept of using a simulation environment when designing an advanced fibre-optic seismometer (FOS) using a field-programmable gate array (FPGA) computing system. The first part of the article presents the advanced requirements regarding the FOS principle of operation, as well as the measurement method using a closed-loop operation. The closed-loop control algorithm is developed using the high-level language C++ and then it is synthesised into an FPGA. The following part of the article describes the simulation environment developed to test the operation of the control algorithm. The environment includes a model of components of the measurement system, delays, and distortions in the signal processing path, and some of the measurement system surroundings. The article ends with a comparison of simulation data with measurements. The obtained results are consistent and prove correctness of the methodology adopted by the authors.

This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.